Variable-to-Variable Run Length Encoding Technique for Testing Low Power VLSI Circuits

Lakshmi K, Robert Theivadas

Abstract

The enhancement of integration capability in semiconductor technology requires a large amount of test data, resulting increase in memory, transition time and test time. In this paper, a novel lossless data compression technique is proposed to reduce test data, time and memory, based on variable to variable run length encoding scheme. In this scheme, a test data is partitioned into variable length test patterns and by applying compression algorithm, the bits are compressed into variable length codes. The encoding technique enhances the test data reduction with a limited number of code words. The compression technique is effective, especially when the runs of 0s and 1s in the test set are high and efficiently compress the data streams which is composed of runs of 0’s and 1’s. The variable to variable run length code algorithm is used to make changes in test vectors and adaptable for compressing precomputed test sets to test the embedded cores of System-on-chip (SOC). The decompression architecture for proposed technique was presented in this paper. Experimental results of ISCAS 85 and ISCAS 89 benchmark circuit’s results in the significant reduction of test data with better compression ratio.