Photonic Approach to Optimize Energy Consumption for On-chip Clos Network

Deepalakshmi B and Maruthachal

Abstract

To meet energy-efficient performance needs, the computation has positioned to parallel computer architectures, such as chip multiprocessors (CMPs), internally interconnected via networks-on-Chip (NoC) to achieve increasing communication needs. To accomplish scaling execution as center include increment to the hundreds future CMPs, all things considered, will require elite, yet vitality productive interconnects. Silicon Nano photonics is a promising swap for electronic on-chip interconnect for its high data transfer capacity and low inactivity, by the by, earlier methods have required high static force for the laser and warm ring tuning. We propose novel Nano photonic NoC (PNoC) design, upgraded for elite and force effectiveness. This paper makes three essential elements: a novel, Nano photonic engineering which isolates the system into subnets for better productivity; an exclusively photonic, inband, appropriated discretion plan; and a channel sharing schematic are using the same waveguides and wavelengths for intervention as information transmission. As a result the interconnection can be reduced latency with increased throughput.