Insights of Trap Level Effect on the Performance of InAlN/GaN High Electron Mobility Transistor (HEMT)

Zhenzhong Yu*, Huiwu Hong, Qig

Abstract

InAlN/GaN high electron mobility transistor (HEMT) structures with appropriate barrier thickness are designed to investigate the effects of trap level on the device’s performance. Based on the two-dimensional drift-diffusion simulation, the influence of five trap levels of 0.3, 0.36, 0.42, 0.6 and 0.95 eV below the conduction band minimum on the DC characteristics of InAlN/GaN HEMTs are described. The results indicate that the depth of trap level obviously affects the drain current and threshold voltage of the devices, which is mainly attributed to the varied trapping rate for electrons at different trap levels according to the Shockley-Read-Hall (SRH) recombination process