Research Article
Dhanushya T and Latha T
Abstract
Radiation induced soft errors are susceptible to most of the electronic products with the development of CMOS technology. A particle striking on any of the electronic products can produce soft errors that can be either single event upset or single event transient. There are various techniques such as FERST, BISER, TMR, DMR, DICE, SEC-DED, DEC-TED, EDAC, PARSHIELD, and STEM for soft error elimination. But these techniques do not provide self-checking capability, and has high area, output corruption. Soft Error and Timing error Tolerant Flip Flop (SETTOFF) is used to conquer these drawbacks. The self-checking is provided at the transition detection part. SETTOFF is designed for normal operation and fault operation. This has higher area overhead than BISER. So BISER by means of self-checking capability has been proposed to conquer the limitations by reducing the area. BISER by means of self-checking can yield better results with reduced area overhead, power and delay compared to SETTOFF architecture and BISER. The architecture is implemented using SPICE and simulation waveforms are obtained.