A 800 MHz-1.1 GHz 1.2 mW Delay Locked Loop with a Closed Loop Duty Cycle Corrector

Boghrati H and Maranjabi Al

Abstract

In this paper a low power delay locked loop with a closed loop duty cycle corrector is proposed. The duty cycle corrector circuit is a dual loop circuit which receives a clock signal with 30%~70% duty cycle and generates a clock signal with 50% ± 2% duty cycle. The power consumption of the overall circuit is 1.2 mW. This circuit is fabricated in 0.18 um CMOS technology. Measurement results show that the RMS jitter of the proposed work is 4 ps at 1 GHz.